BMEN90033 · WEEK 10 · FROM GATES TO A MICROPROCESSOR
From logic gates to a working CPU.
The previous page built the primitives of digital electronics: gates, adders,
multiplexers
and decoders. A microprocessor is what those primitives become once they are wired together at
scale.
The MOS Technology 6502, the processor at the centre of the Apple 1 (1976), is built from 3,510 NMOS
transistors arranged into a register file, an arithmetic logic unit, an instruction decoder and a
control sequencer. This page maps each block onto the gate-level primitives already covered and then
exposes the underlying silicon through a transistor-level simulator of the actual die.
gates → cpuregistersalucontrol unitmos 6502
Use the dots or the arrow keys to advance through the slides.
01historical context
A single-board computer from 1976.
The Apple 1 was the first product of the Apple Computer Company, designed by Steve
Wozniak and offered for sale in July 1976 at a list price of USD 666.66. It shipped as a populated
printed circuit board only. The user supplied a power supply, an ASCII keyboard and a video
monitor. About two hundred units were built between July 1976 and September 1977.
The board carried four kinds of integrated circuit. The MOS Technology 6502 microprocessor handled
computation. A Motorola 6820 Peripheral Interface Adapter (PIA) connected the processor's bus to
the keyboard and the video output. Eight 4-kbit DRAM chips provided 4 kB of system memory. A small
PROM held the 256-byte Wozniak Monitor, the only system software the machine had on power-up.
The choice of CPU was driven by price. The Intel 8080 and Motorola 6800 of the same era sold for
roughly USD 300 each. MOS Technology introduced the 6502 in September 1975 at USD 25 per unit,
cutting the cost of a microprocessor by an order of magnitude and making a personal computer
commercially viable for the first time.
The Apple 1 ran the 6502 at 1.0 MHz, generated by dividing down the same crystal oscillator that
produced the video timing. The successor machine, the Apple II (1977), retained both the 6502 and
the 1.0 MHz clock and used the processor's predictable bus timing to share DRAM access between
the CPU and the video generator without contention.
Apple 1. The populated board mounted in an after-market wooden case, with a
small Panasonic monitor and a parallel ASCII keyboard. Apple supplied only the bare board;
the case, display and keyboard were the user's responsibility.Printed circuit board. The MOS 6502 microprocessor (right, in red) and the
Motorola 6820 Peripheral Interface Adapter (left, in blue) sit at the centre of the board.
The surrounding sockets hold eight 4-kbit DRAM chips that make up the 4 kB of system memory.
Me and Steve at Caffè Macs circa ~2015The designers. Steve Wozniak (left) designed the hardware. Steve Jobs
(right) co-founded the Apple Computer Company and arranged the first commercial order,
of fifty boards from the Byte Shop in Mountain View, California.
02combinational
logic
Decoding instructions with a programmable logic array.
A programmable logic array, or PLA, is a two-level combinational circuit that realises
any boolean function as a sum of products. The first level (the AND-plane) forms product terms from
the inputs and their complements. The second level (the OR-plane) sums chosen product terms onto
each output. Both planes are programmable: a connection placed at any cross-point selects which
signals participate.
The widget on the right is a small PLA with four inputs, eight product-term lines and four outputs.
The vertical rail at the top carries each input and its complement, so eight signals enter the
AND-plane. Each horizontal product line sees a dot at every input it is connected to; the value on
that line is the AND of those signals. A product line with dots on $A_1$ and $\overline{A_0}$, for
example, evaluates to $A_1 \cdot \overline{A_0}$. The OR-plane below works the same way: each output
line reads the OR of the product lines that have dots on it.
The instruction decoder of the MOS 6502 is a PLA of exactly this shape, only larger. The eight bits
of the opcode register feed the AND-plane, around 130 product terms decode the legal opcodes, and
the OR-plane drives the control lines that sequence each instruction. The same primitive that lights
one of four outputs in the demo to the right lights, one of more than a hundred control signals on
the real chip.
Click any cross-point in either plane to toggle a connection. Toggle the input switches at any time
to drive the array. Three presets load real functions: a 2-to-4 decoder, a dual 2:1 multiplexer that
uses $A_2$ and $A_3$ as independent select bits over the same data pair, and a fragment of a 6502
opcode decoder that recognises the low nibbles of LDA #, STA zp and
NOP. The same physical PLA appears in the lower-left of the 6502 die in Section 03.
inputs
preset
no presetClick a preset above to load a real function, or
build one yourself by clicking crossings in either plane.
inputsproduct termsoutputsclick any crossing to weld a connection · lit lines carry a
1
inputs A3..A00000→outputs Y3..Y00000
03visual6502
Transistor-level simulation of the 6502 die.
The simulator below is Visual 6502, by Greg James, Brian Silverman and Barry Silverman. A real chip
was decapsulated, photographed and traced into its 3,510 transistors. The simulator propagates logic
levels through that network one half-cycle at a time, so registers, ALU, decoder and control all
emerge from the underlying transistors rather than from an abstract instruction-set model.
I've written a small "Hello World" routine as an example, which is loaded at $\$0000$. Each iteration
writes a character to the display
register at $\$\text{D012}$ (forwarded to the terminal pane), saves the raw character at
$\$\text{E1}$, and increments a counter at $\$\text{E0}$ so the zero-page memtable shows live
activity.
Use the controls under the chip to run, stop, step or change speed. With animate on, the
logic-state overlay updates every half-cycle, colour-coding clocks, address bus, data bus, registers
and decoder. Clicking a polygon names the underlying node in the status panel.
Every half-cycle re-evaluates the full transistor network until logic levels settle, so the
simulation is slower than a register-transfer-level emulator. Allow several seconds for the chip
layout to render on first load. Everything runs locally in the browser.
Assembly listing· "HELLO, WORLD!" routine, 6502 sourceloaded at $0000
; Apple 1 "Hello World" demo program.
; Walks a null-terminated string at $0020, ORs each byte with $80
; (Apple 1 high-bit ASCII), writes it to the display register at
; $D012, and halts in an infinite loop once the terminator is reached.
; $E0 holds a byte counter; $E1 holds the most recent raw character.*=$0000$0000 A2 00 LDX#$00$0002 B5 20 LOOP:LDA$20,X; load string[X]$0004 F0 0C BEQDONE; null terminator -> exit$0006 85 E1 STA$E1; save raw char to zero page$0008 09 80 ORA#$80; force hi-bit (Apple 1 ASCII)$000A 8D 12 D0 STA$D012; output character to display$000D E6 E0 INC$E0; bump byte counter$000F E8 INX$0010 D0 F0 BNELOOP$0012 4C 12 00 DONE:JMPDONE; halt$0020"HELLO, WORLD!" $0D $00 ; CR + null terminator
Program "Hello World" routine prints to the display registerControls scroll to zoom, drag to pan, slider to change speed
loading 6502 layout...
drag to rotate · scroll to zoom · right-drag to pan
